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| 3.3V 32-175Mbps AnyRateTM CLOCK AND DATA RECOVERY SY87700L FEATURES s s s s s s s s s s s Industrial temperature range (-40C to +85C) 3.3V power supply SONET/SDH/ATM compatible Clock and data recovery from 32Mbps up to 175Mbps NRZ data stream Two on-chip PLLs: one for clock generation and another for clock recovery Selectable reference frequencies Differential PECL high-speed serial I/O Line receiver input: no external buffering needed Link Fault indication 100K ECL compatible I/O Complies with Bellcore, ITU/CCITT and ANSI specifications for applications such as OC-1 and OC-3 Available in 28-pin SOIC and 32-pin EP-TQFP packages DESCRIPTION The SY87700L is a complete Clock Recovery and Data Retiming integrated circuit for data rates from 32Mbps up to 175Mbps NRZ. The device is ideally suited for SONET/SDH/ATM applications and other high-speed data transmission systems. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference. The SY87700L also includes a link fault detection circuit. APPLICATIONS s SONET/SDH/ATM OC-1 and OC-3 s Fast Ethernet s Proprietary architecture up to 175Mbps s BLOCK DIAGRAM PLLR P/N RDOUTP (PECL) RDOUTN 0 1 PHASE/ FREQUENCY DETECTOR LINK FAULT DETECTOR RDINP (PECL) RDINN PHASE DETECTOR CHARGE PUMP VCO RCLKP (PECL) RCLKN CD (PECL) REFCLK (TTL) LFIN (TTL) PHASE/ FREQUENCY DETECTOR CHARGE PUMP VCO 1 0 TCLKP (PECL) TCLKN DIVIDER BY 8, 10, 16, 20 SY87700L DIVSEL 1/2 (TTL) PLLS P/N FREQSEL 1/2/3 (TTL) CLKSEL (TTL) VCC VCCA VCCO GND AnyRateTM is a trademark of Micrel, Inc. Rev.: B Amendment: /0 1 Issue Date: September 2000 Micrel SY87700L PIN CONFIGURATION DIVSEL1 DIVSEL2 VCCA VCCA VCCA 1 LFIN 2 DIVSEL1 3 RDINP 4 RDINN 5 FREQSEL1 6 REFCLK 7 FREQSEL2 8 FREQSEL3 9 N/C 10 PLLSP 11 PLLSN 12 GND 13 GND 14 Top View SOIC Z28-1 28 VCC 27 CD 26 DIVSEL2 25 RDOUTP 24 RDOUTN 23 VCCO 22 RCLKP 21 RCLKN 20 VCCO 19 TCLKP 18 TCLKN 17 CLKSEL 16 PLLRP 15 PLLRN LFIN VCC VCC CD 32 NC RDINP RDINN FREQSEL1 REFCLK FREQSEL2 FREQSEL3 NC 1 2 3 4 5 6 7 8 9 PLLSP 31 30 29 28 27 26 25 24 RDOUTP 23 RDOUTN 22 VCCO Top View EP-TQFP H32-1 21 RCLKP 20 RCLKN 19 VCCO 18 TCLKP 17 TCLKN 10 11 12 13 14 15 16 PLLRN PLLSN GNDA GND PLLRP GND CLKSEL PIN DESCRIPTIONS INPUTS RDINP, RDINN [Serial Data Input] Differential PECL These built-in line receiver inputs are connected to the differential receive serial data stream. An internal receive PLL recovers the embedded clock (RCLK) and data (RDOUT) information. The incoming data rate can be within one of five frequency ranges depending on the state of the FREQSEL pins. See "Frequency Selection" Table. REFCLK [Reference Clock] TTL inputs This input is used as the reference for the internal frequency synthesizer and the "training" frequency for the receiver PLL to keep it centered in the absence of data coming in on the RDIN inputs. CD [Carrier Detect] PECL Input This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. When this input is HIGH the input data stream (RDIN) is recovered normally by the Receive PLL. When this input is LOW the data on the inputs RDIN will be internally forced to a constant LOW, the data outputs RDOUT will remain LOW, the Link Fault Indicator output LFIN forced LOW and the clock recovery PLL forced to look onto the clock frequency generated from REFCLK. FREQSEL1, ..., FREQSEL3 [Frequency Select] TTL Inputs These inputs select the output clock frequency range as shown in the "Frequency Selection" Table. DIVSEL1, DIVSEL2 [Divider Select] TTL Inputs These inputs select the ratio between the output clock frequency (RCLK/TCLK) and the REFCLK input frequency as shown in the "Reference Frequency Selection" Table. CLKSEL [Clock Select] TTL Inputs This input is used to select either the recovered clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency synthesizer (CLKSEL = LOW) to the TCLK outputs. OUTPUTS LFIN [Link Fault Indicator] TTL Output This output indicates the status of the input data stream RDIN. Active HIGH signal is indicating when the internal clock recovery PLL has locked onto the incoming data stream. LFIN will go HIGH if CD is HIGH and RDIN is within the frequency range of the Receive PLL (1000ppm). LFIN is an asynchronous output. 2 Micrel SY87700L RDOUTP, RDOUTN [Receive Data Output] Differential PECL These ECL 100K outputs represent the recovered data from the input data stream (RDIN). This recovered data is specified against the rising edge of RCLK. RCLKP, RCLKN [Clock Output] Differential PECL These ECL 100K outputs represent the recovered clock used to sample the recovered data (RDOUT). TCLKP, TCLKN [Clock Output] Differential PECL These ECL 100K outputs represent either the recovered clock (CLKSEL = HIGH) used to sample the recovered data (RDOUT) or the transmit clock of the frequency synthesizer (CLKSEL = LOW). PLLSP, PLLSN [Clock Synthesis PLL Loop Filter] External loop filter pins for the clock synthesis PLL. PLLRP, PLLRN [Clock Recovery PLL Loop Filter] External loop filter pins for the receiver PLL. POWER & GROUND VCC VCCA VCCO GND N/C Supply Voltage(1) Analog Supply Voltage(1) Output Supply Voltage(1) Ground No Connect NOTE: 1. VCC, VCCA, VCCO must be the same value. FUNCTIONAL DESCRIPTION Clock Recovery Clock Recovery, as shown in the block diagram generates a clock that is at the same frequency as the incoming data bit rate at the Serial Data input. The clock is phase aligned by a PLL so that it samples the data in the center of the data eye pattern. The phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency detector. Output pulses from the detector indicate the required direction of phase correction. These pulses are smoothed by an integral loop filter. The output of the loop filter controls the frequency of the Voltage Controlled Oscillator (VCO), which generates the recovered clock. Frequency stability without incoming data is guaranteed by an alternate reference input (REFCLK) that the PLL locks onto when data is lost. If the Frequency of the incoming signal varies by greater than approximately 1000ppm with respect to the synthesizer frequency, the PLL will be declared out of lock, and the PLL will lock to the reference clock. The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET data signal. This transfer function yields a 30s data stream of continuous 1's or 0's for random incoming NRZ data. The total loop dynamics of the clock recovery PLL provides jitter tolerance which is better than the specified tolerance in GR-253-CORE. Lock Detect The SY87700L contains a link fault indication circuit which monitors the integrity of the serial data inputs. If the received serial data fails the frequency test, the PLL will be forced to lock to the local reference clock. This will maintain the correct frequency of the recovered clock output under loss of signal or loss of lock conditions. If the recovered clock frequency deviates from the local reference clock frequency by more than approximately 1000ppm, the PLL will be declared out of lock. The lock detect circuit will pull the input data stream in an attempt to reacquire lock to data. If the recovered clock frequency is determined to be within approximately 1000ppm, the PLL will be declared in lock and the lock detect output will go active. 3 Micrel SY87700L CHARACTERISTICS Performance The SY87700L PLL complies with the jitter specifications proposed for SONET/SDH equipment defined by the Bellcore Specifications: GR-253-CORE, Issue 2, December 1995 and ITU-T Recommendations: G.958 document, when used with differential inputs and outputs. Input Jitter Tolerance Input jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1dB optical/electrical power penalty. SONET input jitter tolerance requirement condition is the input jitter amplitude which causes an equivalent of 1dB power penalty. Jitter Transfer Jitter transfer function is defined as the ratio of jitter on the output OC-N/STS-N signal to the jitter applied on the input OC-N/STS-N signal versus frequency. Jitter transfer requirements are shown in Figure 2. Jitter Generation The jitter of the serial clock and serial data outputs shall not exceed .01 U.I. rms when a serial data input with no jitter is presented to the serial data inputs. A 0.1 Sinusoidal Input Jitter Amplitude (UI p-p) Jitter Transfer (dB) 15 1.5 -20dB/decade -20dB/decade -20dB/decade -20 Acceptable Range 0.40 f0 f1 f2 Frequency f4 ft fc Frequency OC/STS-N Level 3 f0 (Hz) 10 f1 (Hz) 30 f2 (Hz) 300 f3 (kHz) 6.5 ft (kHz) 65 OC/STS-N Level 3 fc (kHz) 130 Figure 2. Jitter Transfer P (dB) 0.1 Figure 1. Input Jitter Tolerance 4 Micrel SY87700L FREQUENCY SELECTION TABLE FREQSEL1 0 1 1 1 1 0 0 FREQSEL2 1 0 0 1 1 1 0 FREQSEL3 1 0 1 0 1 0 X(2) fVCO/fRCLK 6 8 12 16 24 -- -- fRCLK Data Rates (Mbps) 125 -175 94 - 157 63 - 104 47 - 78 32 - 52 undefined undefined NOTES: 1. SY87700L operates from 32-175MHz. For higher speed applications, the SY87701L operates from 32-1250MHz. 2. X is a DON'T CARE. REFERENCE FREQUENCY SELECTION DIVSEL1 0 0 1 1 DIVSEL2 0 1 0 1 fRCLK/fREFCLK 8 10 16 20 ABSOLUTE MAXIMUM RATINGS(1, 2) Symbol VCC VI IOUT Rating Power Supply Input Voltage Output Current -Continuous -Surge Storage Temperature Operating Temperature Value -0.5 to +7.0 -0.5 to VCC 50 100 -65 to +150 -40 to +85 C C Unit V V mA Tstore LOOP FILTER COMPONENTS(1) TA R5 C3 NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect device reliability. 2. Airflow of 500LFPM recommended. PLLSP PLLSN SONET R5 = 80 C3 = 1.5F (X7R Dielectric) Wide Range R5 = 350 C3 = 0.47F (X7R Dielectric) R6 C4 PLLRP PLLRN SONET R6 = 50 C4 = 1.0F (X7R Dielectric) Wide Range R6 = 680 C4 = 0.47F (X7R Dielectric) NOTE: 1. Suggested Values. Values may vary for different applications. 5 Micrel SY87700L DC ELECTRICAL CHARACTERISTICS Symbol VCC ICC Parameter Power Supply Voltage Power Supply Current Min. 3.15 -- Typ. 3.3 170 Max. 3.45 230 Unit V mA Condition PECL 100K DC ELECTRICAL CHARACTERISTICS VCC = VCCO = VCCA = 3.3V 5%; TA = -40C to + 85C Symbol VIH VIL IIL VOH VOL Parameter Input HIGH Voltage Input LOW Voltage Input LOW Current Output HIGH Voltage Output LOW Voltage Min. VCC - 1.165 VCC - 1.810 0.5 VCC - 1.075 VCC - 1.860 Typ. -- -- -- -- -- Max. VCC - 0.880 VCC - 1.475 -- VCC - 0.830 VCC - 1.570 Unit V V A V V VIN = VIL(Min.) 50 to VCC -2V 50 to VCC -2V Condition TTL DC ELECTRICAL CHARACTERISTICS VCC = VCCO = VCCA = 3.3V 5%; TA = -40C to + 85C Symbol VIH VIL IIH IIL VOH VOL IOS Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Output HIGH Voltage Output LOW Voltage Output Short Circuit Current Min. 2.0 -- -125 -- -300 2.0 -- -15 Typ. -- -- -- -- -- -- -- -- Max. VCC 0.8 -- +100 -- -- 0.5 -100 Unit V V A A A V V mA VIN = 2.7V, VCC = Max. VIN = VCC, VCC = Max. VIN = 0.5V, VCC = Max. IOH = -0.4mA IOL = 4mA VOUT = 0V (maximum 1sec) Condition AC ELECTRICAL CHARACTERISTICS VCC = VCCO = VCCA = 3.3V 5%; TA = -40C to + 85C Symbol fVCO fVCO tACQ tCPWH tCPWL tir tODC tr, tf trskew tDV tDH Parameter VCO Center Frequency VCO Center Frequency Tolerance Acquisition Lock Time REFCLK Pulse Width HIGH REFCLK Pulse Width LOW REFCLK Input Rise Time Output Duty Cycle (RCLK/TCLK) ECL Output Rise/Fall Time Recovered Clock Skew Data Valid Data Hold Min. 750 -- -- 4 4 -- 45 100 -200 1/(2*fRCLK) - 200 1/(2*fRCLK) - 200 6 Typ. -- 5 -- -- -- 0.5 -- -- -- -- -- Max. 1250 -- 15 -- -- 2 55 500 +200 -- -- Unit MHz % s ns ns ns % of UI ps ps ps ps 50 to VCC -2V (20% to 80%) Condition fREFCLK * Byte Rate Nominal Micrel SY87700L TIMING WAVEFORMS tCPWL tCPWH REFCLK tODC tODC RCLK tSKEW tDV tDH RDOUT 7 Micrel SY87700L APPLICATION EXAMPLE GND SW1 VCC 1 2 3 4 5 6 (R17 - R22) 5k x 6 GND Q1 2N2222A R10 LED D2 R9 Ferrite Bead BLM21A102 VCC Stand Off DIODE D1 VCC 1N4148 0.1F VCC 1 Capacitor Pads (1206 format) R1 C1 FB1 22F C9 0.1F C8 C7 22F C6 R7 VCCA VCC 28 CD 27 DIVSEL2 26 RDOUTP 25 RDOUTN 24 VCCO 23 RCLKP 22 RCLKN 21 VCCO 20 TCLKP 19 TCLKN 18 CLKSEL 17 R6 VCC R2 2 LFIN 3 DIVSEL1 4 RDINP 5 RDINN J1 0.1F 0.1F C14 C15 R8 RDIN C2 R3 R4 6 FREQSEL1 7 REFCLK 8 FREQSEL2 9 FREQSEL3 10 N/C 80 R5 See Table 1 GND 0.1F 0.1F C16 C17 0.1F 0.1F C18 C19 LOOP FILTER NETWORK 11 PLLSP 12 PLLSN 13 GND 14 GND C3 1.5F 50 C4 PLLRP 16 1.0F R11 R12 R13 R14 R15 R16 If VCC = +5V: R9 through R14 = 330 If VCC = +3.3V: R9 through R14 = 220 PLLRN 15 REFCLK (TTL) NC GND DPDT Slide Switch XTAL Oscillator 14 0.1F C13 VCC 1 7 C5 Pin 1 (VCCA) 0.1F Pin 28 (VCC) 0.1F Pin 23 (VCCO) 0.1F Pin 20 (VCCO) 0.1F VCC 120 R23 8 C10 C11 C12 For AC coupling only C1 = C2 = 0.1F R1 = R2 = 680 R3 = R4 = 1k Table 1. For DC mode only C1 = C2 = Shorted R1 = R2 = 130 R3 = R4 = 82 NOTES: 1. For VCC = 3.3V R8 = 12k; R = 130 2. For VCC = 5.0V R8 = 24k; R9 = 200 8 Micrel SY87700L Material List For Bypass and AC coupling capacitor, high quality factor (High Q) capacitors are recommended. This will optimize the performance of the device in high frequency domain. The suggested dielectric characteristics for these capacitors are NPO and/or COG. AVX is a suggested provider of electronic components. www.avxcorp.com Description SY87700L/SY87700V/SY87701L/SY87701V 80 1.5F 50 1.0F 5k or 4.7k 330 or 220 (see schematic) 4.7K 130 12k 12k 120 0.1F Tantalum, 22F, 16V 0.1F Murata BLM21A102F 1N4148 Johnson SMAs, ID#142-0701-201 6-pin Dip switch U1 PLLS+, R5 PLLS-, C3 PLLR+, R6 PLLR-, C4 Component Part No.(1, 2) Pull Up Resistor x 6, R17 - R22 Output Pull Down Resistor, R11 - R16 Pull Up Resistor, R7 Pull Up Resistor, R9 Pull Down Resistor, R8 R10 R23 AC Coupling Capacitors x 6, C1, C2, C14 - C19 Decoupling Capacitor, C6, C8 Decoupling Capacitors x 7, C5, C7, C9 - C13 Ferrite Bead, FB1 Diode, D1 SMAs x 9 SW1 DPDT Slide Switch LED NOTES: 1. For VCC = 3.3V R8 = 12k; R = 130 2. For VCC = 5.0V R8 = 24k; R9 = 200 PRODUCT ORDERING CODE Ordering Code SY87700LZI SY87700LHI *Contact factory for availability. Package Type Z28-1 H32-1* Operating Range Industrial Industrial 9 Micrel SY87700L 28 LEAD SOIC .300" WIDE (Z28-1) Rev. 02 10 Micrel SY87700L 32 LEAD EPAD TQFP (DIE UP) (H32-1) Rev. 01 11 Micrel SY87700L MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 12 |
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